1. Field of the Invention
This invention relates to an improvement of a semiconductor memory device, such as a non-volatile memory cell or a DRAM cell, which has a large capacitance between gate electrodes and a low writing voltage.
2. Description of the Related Art
A conventional non-volatile semiconductor memory device such as a PROM has a memory cell structure as shown in FIGS. 1 and 2. As is shown in FIG. 1, a p-type semiconductor substrate 1 has a field oxide film 3 formed thereon to serve as an element-separating region for separating an element region 2. FIG. 2 shows the cross section of a two-layered gate electrode portion of the memory cell structure taken along the channel length direction thereof. As is shown in FIG. 2, the element region 2 has n+-type source and drain regions 4 and 5 which are electrically separated from each other, and a channel region 11 extending therebetween. A first gate electrode 7 serving as a floating gate electrode and made, for example, of polycrystal silicon doped with an impurity is formed on the element region 2, with a first gate insulating film 6 interposed therebetween. A second gate electrode 9 serving as a control gate electrode made, for example, of polycrystal silicon doped with an impurity is stacked on the first gate electrode 7, with a second gate insulating film 8 interposed therebetween. Opposite ends of the first gate electrode 7 extend in the channel width direction and partially overlap with the field oxide film 3, as is shown in FIG. 1. An insulating film 10 is formed on the exposed side surfaces of the first gate electrode 7 and on the second gate electrode 9, as is shown in FIG. 2. In the case of this PROM, a high voltage is applied to the n+-type drain region 5 to thereby inject and accumulate hot electrons generated in the channel region 11, into the first gate electrode 7 through the first gate insulating film 6, so as to vary the threshold voltage Vth of the cell and thus enable the cell to maintain its memory function.
FIG. 3 shows an electrical circuit employed in the PROM shown in FIGS. 1 and 2 and used at the time of writing. The voltage V.sub.FG of the floating gate electrode 7 and the voltage V.sub.CG of the control gate electrode 9 have the following relationship: EQU V.sub.FG =C2.multidot.V.sub.CG /C.sub.T +C.sub.3 .multidot.V.sub.D /C.sub.T( 1) EQU C.sub.T =C.sub.1 +C.sub.2 +C.sub.3 ( 2)
where C.sub.1 represents a capacitance between the substrate 1 and the floating gate electrode 7, C.sub.2 a capacitance between the floating gate electrode 7 and the control gate electrode 9, C.sub.3 the capacitance of an overlapping portion between the drain region 5 and the floating gate electrode 7, and V.sub.D a drain voltage.
The so-called writing voltage of the PROM is determined on the basis of the voltage VFG of the floating gate electrode 7, the voltage VFG actually being controlled by the voltage V.sub.CG of the control gate electrode 9. As a result, the proportional coefficient between V.sub.FG and V.sub.CG is C.sub.2 /C.sub.T, and writing can be performed at low voltage only if the capacitance C.sub.2 between the floating gate electrode 7 and the control gate electrode 9 is large.
In the prior art, the writing voltage applied to the control gate electrode of a 1-Mbit EPROM device is as high as 12.5 V. A reduction in writing voltage will be required in accordance with further scaling-down of semiconductor elements in near future. Reducing the thickness of the second gate insulating film 8 shown in FIG. 1 is one possible method for increasing the capacitance C.sub.2 between the gate electrodes. In practice, however, it is difficult to accomplish this without degrading required characteristics of the film.